Thin Film Transistors (TFTs) have been used in a variety of electro-optical devices, such as liquid crystal display devices and semiconductor devices. In a TFT, the quality of a gate insulating layer has an extremely important effect on the electrical properties of the TFT. Using a gate insulating material with a high-quality and a high K-value (i.e., dielectric constant) can improve the device performances of a TFT to a large extent, for example, it can lower a threshold voltage, increase a Ion/Ioff ratio and decrease a sub-threshold swing.
Conventional TFT devices use processes such as chemical vapor deposition (CVD) and sputtering to deposit a SiO2 or SiNx film as a gate insulating layer. For example, a non-patent document 1 discloses a method for preparing a gate insulating layer with a process of using tetraethyl orthosilicate (TEOS). However, this method is still a CVD process, and the formed gate insulating thin layer has a relatively loosen texture and an unsatisfactory insulating property (only achieving approximately 5.6×106 V·cm−1) due to a relatively low formation temperature, which will affect the device performances due to a too large leakage current for the TFT device. If the gate insulating layer is thickened, the operating voltage of the device may be increased, and the process time may be extended.
Therefore, there is still a need in the art for an improved method for manufacturing a TFT, especially a gate insulating layer.
Non-Patent Document 1: Kow-Ming Chang, et al., “Electrical Characteristics of Low Temperature Polysilicon TFT With a Novel TEOS/Oxynitride Stack Gate Dielectric”, IEEE ELECTRON DEVICE LETTERS, Vol. 24, No. 8, August 2003.